Layout is an important part of design. Our design service professionals engage in projects from single building blocks to high performance ASICs. Highly experienced in leading edge technology nodes （16nm FinFET process etc.), we can provide you with expertise in Std Cell/Library design, IO/Memory design, PLL design and Custom Analog design.
Good Practice in Design for Test methodology during SoC design and verification can improve time to market and reduce manufacturing costs. Chipsea’s DfT consultancy delivers testable silicon with optimal test time. As part of an outsourced project engagement, or as an embedded member of your design team, Chipsea can provide the specialist DfT consulting expertise to meet your target test coverage.
Physical design of a large SoC has become increasingly challenging in advance technology nodes. As well as the difficulty of meeting more challenging Performance-Power-Area (PPA) requirements, you have to contend with additional constraints such as On-Chip-Variation (OCV), Design-for-Manufacturing (DfM) and Design-for-Test (DfT). Design teams also have to face the complexity of hierarchical design which may extend to in excess of 100 sub-blocks. Time-to-market is more critical than ever in an extremely competitive marketplace that requires the minimum amount of iterations between design and silicon. As a consequence of all of these challenges, it is vital that the design flow is robust enough to incorporate Engineering-Change-Order (ECO) at the late stage of the project, pre or post manufacturing.
Chipsea addresses the complex requirements of today’s SoC projects by utilising our award winning multi-platform design flow Helium-8P, together with our management methodology Neon, which have both been proven on large designs in sub-deep micro technology nodes, with multiple-location design teams of up to 30 engineers.
Design Verification of modern digital IC’s is challenging, often on the critical path for a project and consuming many costly resources. The consequences of getting this task wrong can have major implications on your business, such as delays in getting your product to market, costly re-spins or even product field failures. It is important to ensure the design has been verified as much as possible within the time and cost constraints of the project. This necessitates starting verification as early in the design cycle as possible, a “shift left” in the verification task, removing hardware and software bugs where they have the least impact. Chipsea’s verification team are skilled in the broad range of advanced design verification and debug methodologies for SoC and IP functional verification with SystemVerilog UVM, power integrity verification, formal verification and HW acceleration enabling your verification projects to “shift left”.